View AD9637BCPZ-80_4417688.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

octal, 12-bit, 40/80 msps, serial lvds, 1.8 v analog-to-digital converter data sheet ad9637 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2011 analog devices, inc. all rights reserved. features low power: 60 mw per channel at 80 msps with scalable power options snr = 71.5 dbfs (to nyquist) sfdr = 92 dbc (to nyquist) dnl = 0.4 lsb (typical), inl = 0.5 lsb (typical) serial lvds (ansi-644, default) low power, reduced signal option (similar to ieee 1596.3) data and frame clock outputs 650 mhz full power analog bandwidth 2 v p-p differential input voltage range 1.8 v supply operation serial port control full chip and individual channel power-down modes flexible bit orientation built-in and custom digital test pattern generation programmable clock and data alignment programmable output resolution standby mode applications medical imaging and nondestructive ultrasound portable ultrasound and digital beam-forming systems quadrature radio receivers diversity radio receivers optical networking test equipment general description the ad9637 is an octal, 12-bit, 40/80 msps analog-to-digital converter (adc) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. the product operates at a conversion rate of up to 80 msps and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. the adc requires a single 1.8 v power supply and lvpecl-/ cmos-/lvds-compatible sample rate clock for full performance operation. no external reference or driver components are required for many applications. the adc automatically multiplies the sample rate clock for the appropriate lvds serial data rate. a data clock output (dco) for capturing data on the output and a frame clock output (fco) for signaling a new output byte are provided. individual channel power-down is supported and typically consumes less than 2 mw when all channels are disabled. the adc contains several features designed to maximize flexibility and minimize system cost, such as programmable functional block diagram adc 12 serial lvds d+ a d? a vin+ a a v dd ad9637 vin? a adc 12 serial lvds d+ b d? b vin+ b vin? b adc 12 serial lvds d+ c d? c vin+ c vin? c adc 12 serial lvds d+ d d? d vin+ d vin? d adc 12 serial lvds d+ e d? e vin+ e vin? e adc 12 serial lvds d+ f d? f vin+ f vin? f adc 12 serial lvds d+ g d? g vin+ g vin? g adc 12 serial lvds data rate multiplier serial port interface ref select d+ h fco+ fco? dco+ dco? d? h vin+ h vin? h vref vcm 1.0v sync sense pdwn dr v dd rbias agnd csb clk+ clk? sdio/ dfs sclk/ dtp 10215-001 figure 1. clock and data alignment and programmable digital test pattern generation. the available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (spi). the ad9637 is available in a rohs-compliant, 64-lead lfcsp. it is specified over the industrial temperature range of ?40c to +85c. this product is protected by a u.s. patent. product highlights 1. small footprint. eight adcs are contained in a small, space-saving package. 2. low power of 60 mw/channel at 80 msps with scalable power options. 3. ease of use. a data clock output (dco) is provided that operates at frequencies of up to 480 mhz and supports double data rate (ddr) operation. 4. user flexibility. the spi control offers a wide range of flexible features to meet specific system requirements. 5. pin compatible with the ad9257 (14-bit octal adc).
ad9637 data sheet rev. 0 | page 2 of 40 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? product highlights ........................................................................... 1 ? table of contents .............................................................................. 2 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? dc specifications ......................................................................... 3 ? ac specifications.......................................................................... 4 ? digital specifications ................................................................... 5 ? switching specifications .............................................................. 6 ? timing specifications .................................................................. 6 ? absolute maximum ratings............................................................ 8 ? thermal characteristics .............................................................. 8 ? esd caution.................................................................................. 8 ? pin configuration and function descriptions............................. 9 ? typical performance characteristics ........................................... 11 ? ad9637-80 .................................................................................. 11 ? ad9637-40 .................................................................................. 14 ? equivalent circuits ......................................................................... 17 ? theory of operation ...................................................................... 18 ? analog input considerations.................................................... 18 ? voltage reference ....................................................................... 19 ? clock input considerations...................................................... 20 ? power dissipation and power-down mode ........................... 22 ? digital outputs and timing ..................................................... 23 ? built-in output test modes .......................................................... 27 ? output test modes..................................................................... 27 ? serial port interface (spi).............................................................. 28 ? configuration using the spi..................................................... 28 ? hardware interface..................................................................... 29 ? configuration without the spi ................................................ 29 ? spi accessible features.............................................................. 29 ? memory map .................................................................................. 30 ? reading the memory map register table............................... 30 ? memory map register table..................................................... 31 ? memory map register descriptions........................................ 34 ? applications information .............................................................. 36 ? design guidelines ...................................................................... 36 ? power and ground recommendations ................................... 36 ? exposed pad thermal heat slug recommendations............ 36 ? vcm............................................................................................. 36 ? reference decoupling................................................................ 36 ? spi port ........................................................................................ 36 ? outline dimensions ....................................................................... 37 ? ordering guide .......................................................................... 37 ? revision history 10/11revision 0: initial version
data sheet ad9637 rev. 0 | page 3 of 40 specifications dc specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 1. ad9637-40 ad9637-80 parameter 1 temp min typ max min typ max unit resolution 14 14 bits accuracy no missing codes full guaranteed guaranteed offset error full ?0.6 ?0.3 +0.1 ?0.7 ?0.3 +0.1 % fsr offset matching full 0.0 0.2 0.6 0.0 0.2 0.6 % fsr gain error full ?8.0 ?2.1 +2.0 ?7.0 ?3.2 +1.0 % fsr gain matching full ?1.0 +1.7 +5.0 ?1.0 +2.3 +6.0 % fsr differential nonlinearity (dnl) full ?0.8 0.3 +0.8 ?0.8 0.4 +0.8 lsb integral nonlinearity (inl) full ?1.0 0.4 +1.0 ?1.2 0.5 +1.2 lsb temperature drift offset error full 2 2 ppm/c internal voltage reference output voltage (1 v mode) full 0.98 0.99 1.01 0.98 0.99 1.01 v load regulation at 1.0 ma (v ref = 1 v) full 2 2 mv input resistance full 7.5 7.5 k input referred noise v ref = 1.0 v 25c 0.36 0.49 lsb rms analog inputs differential input voltage (v ref = 1 v) full 2 2 v p-p common-mode voltage full 0.9 0.9 v differential input resistance 5.2 5.2 k differential input capacitance full 3.5 3.5 pf power supply avdd full 1.7 1.8 1.9 1.7 1.8 1.9 v drvdd full 1.7 1.8 1.9 1.7 1.8 1.9 v i avdd (eight channels) full 142 151 221 234 ma i drvdd (eight channels, ansi-644 mode) full 51 79 58 85 ma i drvdd (eight channels, reduced range mode) 25c 36 43 ma total power consumption total power dissipation (eight channels, ansi-644 mode) full 347 414 502 574 mw total power dissipation (eight channels, reduced range mode) 25c 320 475 mw power-down dissipation 25c 1 1 mw standby dissipation 2 25c 72 98 mw 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 can be controlled via the spi.
ad9637 data sheet rev. 0 | page 4 of 40 ac specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 2. ad9637-40 ad9637-80 parameter 1 temp min typ max min typ max unit signal-to-noise ratio (snr) f in = 9.7 mhz 25c 72.0 71.5 dbfs f in = 19.7 mhz full 70.0 72.0 71.0 71.5 dbfs f in = 30.5 mhz 25c 72.0 71.5 dbfs f in = 63.5 mhz 25c 71.5 dbfs f in = 69.5 mhz 25c 71.5 dbfs f in = 123.5 mhz 25c 70.5 dbfs signal-to-noise and distortion ratio (sinad) f in = 9.7 mhz 25c 71.0 70.5 dbfs f in = 19.7 mhz full 69.0 71.0 70.0 70.5 dbfs f in = 30.5 mhz 25c 71.0 70.5 dbfs f in = 63.5 mhz 25c 70.5 dbfs f in = 69.5 mhz 25c 70.5 dbfs f in = 123.5 mhz 25c 69.5 dbfs effective number of bits (enob) f in = 9.7 mhz 25c 11.5 11.4 bits f in = 19.7 mhz full 11.2 11.5 11.3 11.4 bits f in = 30.5 mhz 25c 11.5 11.4 bits f in = 63.5 mhz 25c 11.4 bits f in = 69.5 mhz 25c 11.4 bits f in = 123.5 mhz 25c 11.3 bits spurious-free dynamic range (sfdr) f in = 9.7 mhz 25c 96 93 dbc f in = 19.7 mhz full 78 95 78 92 dbc f in = 30.5 mhz 25c 96 92 dbc f in = 63.5 mhz 25c 93 dbc f in = 69.5 mhz 25c 89 dbc f in = 123.5 mhz 25c 88 dbc worst harmonic (second or third) f in = 9.7 mhz 25c ?99 ?96 dbc f in = 19.7 mhz full ?96 ?78 ?92 ?78 dbc f in = 30.5 mhz 25c ?98 ?92 dbc f in = 63.5 mhz 25c ?95 dbc f in = 69.5 mhz 25c ?89 dbc f in = 123.5 mhz 25c ?89 dbc worst other (excluding second or third) f in = 9.7 mhz 25c ?98 ?97 dbfs f in = 19.7 mhz full ?98 ?86 ?97 ?86 dbfs f in = 30.5 mhz 25c ?98 ?97 dbfs f in = 63.5 mhz 25c ?97 dbfs f in = 69.5 mhz 25c ?97 dbfs f in = 123.5 mhz 25c ?92 dbfs two-tone intermodulation distortion (imd) ain1 and ain2 = ?7.0 dbfs f in1 = 8 mhz, f in2 = 10 mhz 25c 93 dbc f in1 = 30 mhz, f in2 = 32 mhz 25c 85 dbc
data sheet ad9637 rev. 0 | page 5 of 40 ad9637-40 ad9637-80 crosstalk 25c ?98 ?96 db crosstalk (overrange condition) 2 25c ?89 ?89 db analog input bandwidth, full power 25c 650 650 mhz 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 overrange condition is specified with 3 db of the full-scale input range. digital specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 3. parameter 1 temp min typ max unit clock inputs (clk+, clk?) logic compliance cmos/lvds/lvpecl differential input voltage 2 full 0.2 3.6 v p-p input voltage range full agnd ? 0.2 avdd + 0.2 v input common-mode voltage full 0.9 v input resistance (differential) 25c 15 k input capacitance 25c 4 pf logic inputs (pdwn, sync, sclk) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 30 k input capacitance 25c 2 pf logic input (csb) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 2 pf logic input (sdio) logic 1 voltage full 1.2 avdd + 0.2 v logic 0 voltage full 0 0.8 v input resistance 25c 26 k input capacitance 25c 5 pf logic output (sdio) 3 logic 1 voltage (i oh = 800 a) full 1.79 v logic 0 voltage (i ol = 50 a) full 0.05 v digital outputs (d x), ansi-644 logic compliance lvds differential output voltage (v od ) full 247 350 454 mv output offset voltage (v os ) full 1.13 1.21 1.38 v output coding (default) twos complement digital outputs (d x), low power, reduced signal option logic compliance lvds differential output voltage (v od ) full 150 200 250 mv output offset voltage (v os ) full 1.13 1.21 1.38 v output coding (default) twos complement 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 this is specified for lvds and lvpecl only. 3 this is specified for 13 sdio/dfs pins sharing the same connection.
ad9637 data sheet rev. 0 | page 6 of 40 switching specifications avdd = 1.8 v, drvdd = 1.8 v, 2 v p-p differential input, 1.0 v internal reference, ain = ?1.0 dbfs, unless otherwise noted. table 4. parameter 1 , 2 temp min typ max unit clock 3 input clock rate full 10 640 mhz conversion rate full 10 40/80 msps clock pulse width high (t eh ) full 12.5/6.25 ns clock pulse width low (t el ) full 12.5/6.25 ns output parameters 3 propagation delay (t pd ) full 2.3 ns rise time (t r ) (20% to 80%) full 300 ps fall time (t f ) (20% to 80%) full 300 ps fco propagation delay (t fco ) full 1.5 2.3 3.1 ns dco propagation delay (t cpd ) 4 full t fco + (t sample /24) ns dco to data delay (t data ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps dco to fco delay (t frame ) 4 full (t sample /24) ? 300 (t sample /24) (t sample /24) + 300 ps data to data skew (t data-max ? t data-min ) full 50 200 ps wake-up time (standby) 25c 35 s wake-up time (power-down) 5 25c 375 s pipeline latency full 16 clock cycles aperture aperture delay (t a ) 25c 1 ns aperture uncertainty (jitter) 25c 0.1 ps rms out-of-range recovery time 25c 1 clock cycles 1 see the an-835 application note , understanding high speed adc testing and evaluation , for definitions and for details on how these tests were completed. 2 measured on standard fr-4 material. 3 can be adjusted via the spi. 4 t sample /24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. t sample = 1/f s . 5 wake-up time is defined as the time required to return to normal operation from power-down mode. timing specifications table 5. parameter description limit unit sync timing requirements t ssync sync to rising edge of clk+ setup time 0.24 ns typ t hsync sync to rising edge of clk+ hold time 0.40 ns typ spi timing requirements see figure 61 t ds setup time between the data and th e rising edge of sclk 2 ns min t dh hold time between the data and the rising edge of sclk 2 ns min t clk period of the sclk 40 ns min t s setup time between csb and sclk 2 ns min t h hold time between csb and sclk 2 ns min t high sclk pulse width high 10 ns min t low sclk pulse width low 10 ns min t en_sdio time required for the sdio pin to switch from an input to an output relative to the sclk falling edge (not shown in figure 61 ) 10 ns min t dis_sdio time required for the sdio pin to switch from an output to an input relative to the sclk rising edge (not shown in figure 61 ) 10 ns min
data sheet ad9637 rev. 0 | page 7 of 40 timing diagrams dco? dco+ d? x d+ x fco? fco+ clk? clk+ msb n ? 17 d10 n ? 17 d9 n ? 17 d8 n ? 17 d7 n ? 17 d6 n ? 17 d5 n ? 17 d4 n ? 17 d3 n ? 17 d2 n ? 17 d1 n ? 17 d0 n ? 17 d10 n ? 16 msb n ? 16 n ? 1 n t data t frame t fco t pd t cpd t eh t a t el 05967-002 vin x figure 2. word-wise ddr, 1 frame, 12-bit output mode (default) 10215-003 dco+ dco? clk+ fco+ fco? d? x d+ x clk? msb n ? 17 n ? 1 n d8 n ? 17 d7 n ? 17 d5 n ? 17 t data t frame t fco t pd d4 n ? 17 d6 n ? 17 d8 n ? 16 d7 n ? 16 d5 n ? 16 d6 n ? 16 d3 n ? 17 d1 n ? 17 msb n ? 16 d0 n ? 17 d2 n ? 17 t cpd t eh t a t el vin x figure 3. word-wise ddr, 1 frame, 10-bit output mode sync clk+ t hsync t ssync 10215-004 figure 4. sync input timing requirements
ad9637 data sheet rev. 0 | page 8 of 40 absolute maximum ratings table 6. parameter rating electrical avdd to agnd ?0.3 v to +2.0 v drvdd to agnd ?0.3 v to +2.0 v digital outputs (d x, dco+, dco?, fco+, fco?) to agnd ?0.3 v to +2.0 v clk+, clk? to agnd ?0.3 v to +2.0 v vin+ x, vin? x to agnd ?0.3 v to +2.0 v sclk/dtp, sdio/dfs, csb to agnd ?0.3 v to +2.0 v sync, pdwn to agnd ?0.3 v to +2.0 v rbias to agnd ?0.3 v to +2.0 v vref, sense to agnd ?0.3 v to +2.0 v environmental operating temperature range (ambient) ?40c to +85c maximum junction temperature 150c lead temperature (soldering, 10 sec) 300c storage temperature range (ambient) ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal characteristics the exposed paddle must be soldered to the ground plane for the lfcsp package. soldering the exposed paddle to the printed circuit board (pcb) increases the reliability of the solder joints and maximizes the thermal capability of the package. table 7. thermal resistance package type airflow velocity (m/sec) ja 1, 2 jc 1, 3 jb 1, 4 ? jt 1, 2 unit 64-lead lfcsp 9 mm 9 mm (cp-64-4) 0 22.3 1.4 n/a 0.1 c/w 1.0 19.5 n/a 11.8 0.2 c/w 2.5 17.5 n/a n/a 0.2 c/w 1 per jedec 51-7, plus jede c 25-5 2s2p test board. 2 per jedec jesd51-2 (still air) or jedec jesd51-6 (moving air). 3 per mil-std 883, method 1012.1. 4 per jedec jesd51-8 (still air). typical ja is specified for a 4-layer pcb with a solid ground plane. as shown table 7, airflow improves heat dissipation, which reduces ja . in addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces ja . esd caution
data sheet ad9637 rev. 0 | page 9 of 40 pin configuration and fu nction descriptions 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 d? g d+ g d? f d+ f d? e d+ e dco? dco+ fco? fco+ d? d d+ d d? c d+ c d? b d+ b 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 vin+ f vin? f avdd vin? e vin+ e avdd sync vcm vref sense rbias vin+ d vin? d avdd vin? c vin+ c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 avdd vin+ g vin? g avdd vin? h vin+ h avdd avdd clk? clk+ avdd avdd dnc drvdd d? h d+ h avdd vin+ b vin? b avdd vin? a vin+ a avdd pdwn csb sdio/dfs sclk/dtp avdd dnc drvdd d+ a d? a 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ad9637 top view (not to scale) notes 1. dnc = do not connect. do not connect to this pin. 2. the exposed pad must be connected to analog ground. pin 1 indicator 10215-005 figure 5. pin configuration, top view table 8. pin function descriptions pin no. mnemonic description 0, ep agnd, exposed pad analog ground, exposed pad. the exposed thermal pad on the bottom of the package provides the analog ground for the part. this exposed pad must be connected to analog ground for proper operation. 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 avdd 1.8 v analog supply. 13, 36 dnc do not connect. do not connect to this pin. 14, 35 drvdd 1.8 v digital output driver supply. 2, 3 vin+ g, vin? g adc g analog inp ut true, adc g analog input complement. 5, 6 vin? h, vin+ h adc h analog inp ut complement, adc h analog input true. 9, 10 clk?, clk+ input clock complement, input clock true. 15, 16 d? h, d+ h adc h digital output complement, adc h digital output true. 17, 18 d? g, d+ g adc g digital output complement, adc g digital output true. 19, 20 d? f, d+ f adc f digital output complement, adc f digital output true. 21, 22 d? e, d+ e adc e digital output complement, adc e digital output true. 23, 24 dco?, dco+ data clock digital output complement, data clock digital output true. 25, 26 fco?, fco+ frame clock digital output complement, frame clock digital output true. 27, 28 d? d, d+ d adc d digital output complement, adc d digital output true. 29, 30 d? c, d+ c adc c digital output complement, adc c digital output true. 31, 32 d? b, d+ b adc b digital output complement, adc b digital output true. 33, 34 d? a, d+ a adc a digital output complement, adc a digital output true. 38 sclk/dtp serial clock (sclk)/digital test pattern (dtp). 39 sdio/dfs serial data input/output (sdio)/data format select (dfs). 40 csb chip select bar. 41 pdwn power-down. 43, 44 vin+ a, vin? a adc a analog inp ut true, adc a analog input complement. 46, 47 vin? b, vin+ b adc b analog inp ut complement, adc b analog input true. 49, 50 vin+ c, vin? c adc c analog inp ut true, adc c analog input complement.
ad9637 data sheet rev. 0 | page 10 of 40 pin no. mnemonic description 52, 53 vin? d, vin+ d adc d analog inp ut complement, adc d analog input true. 54 rbias sets analog current bi as. connect to 10 k (1% tolerance) resistor to ground. 55 sense reference mode selection. 56 vref voltage reference input/output. 57 vcm analog output voltage at midsupply. sets common mode of the analog inputs. 58 sync digital input. sync input to cl ock divider. 30 k internal pull-down. 60, 61 vin+ e, vin? e adc e analog inp ut true, adc e analog input complement. 63, 64 vin? f, vin+ f adc f analog inp ut complement, adc f analog input true.
data sheet ad9637 rev. 0 | page 11 of 40 typical performance characteristics ad9637-80 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 4 8 12 16 20 24 28 32 36 amplitude (dbfs) frequency (mhz) 80msps 9.7mhz at ?1dbfs snr = 70.8db (71.8dbfs) sfdr = 92.7dbc 10215-006 figure 6. single-tone 16k fft with f in = 9.7 mhz, f sample = 80 msps 4 8 12 16 20 24 28 32 36 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 80msps 63.5mhz at ?1dbfs snr = 70.5db (71.5dbfs) sfdr = 93.2dbc 10215-007 figure 7. single-tone 16k fft with f in = 63.5 mhz, f sample = 80 msps 4 8 12 16 20 24 28 32 36 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 10215-008 f2?f1 2f1 ? f2 2f2 ? f1 + 2f1 + f2 f1 + f2 2f2 + f1 figure 8. two-tone 16k fft with f in1 = 30 mhz and f in2 = 32 mhz, f sample = 80 msps 4 8 12 16 20 24 28 32 36 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 80msps 19.7mhz at ?1dbfs snr = 70.7db (71.7dbfs) sfdr = 90.1dbc 10215-009 figure 9. single-tone 16k fft with f in = 19.7 mhz, f sample = 80 msps 4 8 12 16 20 24 28 32 36 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 80msps 30.5mhz at ?1dbfs snr = 70.7db (71.7dbfs) sfdr = 90.7dbc 10215-109 figure 10. single-tone 16k fft with f in = 30.5 mhz, f sample = 80 msps 4 8 12 16 20 24 28 32 36 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 80msps 123.5mhz at ?1dbfs snr = 69.6db (70.6dbfs) sfdr = 90.3dbc 10215-010 figure 11. single-tone 16k fft with f in = 123.5 mhz, f sample = 80 msps
ad9637 data sheet rev. 0 | page 12 of 40 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?6 ?18 ?30 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) imd3 (dbfs) 10215-011 sfdr (dbc) sfdr (dbfs) imd3 (dbc) figure 12. two-tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 30 mhz and f in2 = 32 mhz, f sample = 80 msps 120 0 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdrfs sfdr snrfs snr 0 20 40 60 80 100 ?70 ?60 ?50 ?40 ?30 ?20 ?10 10215-012 figure 13. snr/sfdr vs. analog input level, f in = 9.7 mhz, f sample = 80 msps 105 20 30 40 50 60 70 snr/sfdr (dbfs/dbc) sample frequency (msps) 70 75 80 85 90 95 100 sfdr snrfs 80 10215-013 figure 14. snr/sfdr vs. encode, f in = 19.7 mhz 105 70 ?40 85 snr/sfdr (dbfs/dbc) temperature (c) 75 80 85 90 95 100 ?15 10 35 60 sfdr (dbc) snr (dbfs) 10215-014 figure 15. snr/sfdr vs. temperature, f in = 9.7 mhz, f sample = 80 msps 110 100 0 0 200 snr/sfdr (dbfs/dbc) input frequency (mhz) 70 10 20 30 40 50 60 80 90 100 50 150 sfdr (dbc) snr (dbfs) 10215-015 figure 16. snr/sfdr vs. f in , f sample = 80 msps 20 30 40 50 60 70 80 105 snr/sfdr (dbfs/dbc) sample frequency (msps) 65 70 75 80 85 90 95 100 sfdr snrfs 10215-016 figure 17. snr/sfdr vs. encode, f in = 30.5 mhz
data sheet ad9637 rev. 0 | page 13 of 40 0 100,000 200,000 300,000 400,000 500,000 600,000 700,000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 number of hits output code 0.491 lsb rms 10215-017 figure 18. input referred noise histogram, f sample = 80 msps 2.0 ?2.0 0 inl (lsb) output code ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 400 800 1600 1200 2000 2400 2800 3200 3600 4000 10215-018 figure 19. inl, f in = 9.7 mhz, f sample = 80 msps 1.0 ?1.0 0 dnl (lsb) output code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 500 1000 2000 1500 2500 3000 3500 4000 10215-019 figure 20. dnl, f in = 9.7 mhz, f sample = 80 msps
ad9637 data sheet rev. 0 | page 14 of 40 ad9637-40 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 2 4 6 8 10 12 14 16 18 amplitude (dbfs) frequency (mhz) 40msps 9.7mhz at ?1dbfs snr = 71.0db (72.0dbfs) sfdr = 96.9dbc 10215-020 figure 21. single-tone 16k fft with f in = 9.7 mhz, f sample = 40 msps 2 4 6 8 10 12 14 16 18 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 40msps 30.5mhz at ?1dbfs snr = 70.9db (7.19dbfs) sfdr = 95.87dbc 10215-021 figure 22. single-tone 16k fft with f in = 30.5 mhz, f sample = 40 msps 2 4 6 8 10 12 14 16 18 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 10215-022 f2 ? f1 2f2 ? f1 2f1 ? f2 2f2 + f1 f1 + f2 + 2f1 + f2 figure 23. two-tone 16k fft with f in1 = 8 mhz and f in2 = 10 mhz, f sample = 40 msps 2 4 6 8 10 12 14 16 18 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 40msps 19.7mhz at ?1dbfs snr = 70.9db (71.9dbfs) sfdr = 91.0dbc 10215-023 figure 24. single-tone 16k fft with f in = 19.7 mhz, f sample = 40 msps 2 4 6 8 10 12 14 16 18 0 ?15 ?30 ?45 ?75 ?60 ?105 ?90 ?120 ?135 amplitude (dbfs) frequency (mhz) 40msps 69.5mhz at ?1dbfs snr = 70.5db (71.5dbfs) sfdr = 88.6dbc 10215-024 figure 25. single-tone 16k fft with f in = 69.5 mhz, f sample = 40 msps 0 ?20 ?40 ?60 ?80 ?100 ?120 ?90 ?78 ?66 ?54 ?42 ?6 ?18 ?30 sfdr/imd3 (dbc/dbfs) input amplitude (dbfs) sfdr (dbc) sfdr (dbfs) imd3 (dbc) imd3 (dbfs) 10215-025 figure 26. two-tone sfdr/imd3 vs. input amplitude (ain) with f in1 = 30 mhz and f in2 = 32 mhz, f sample = 40 msps
data sheet ad9637 rev. 0 | page 15 of 40 0 ?70 ?60 ?50 ?40 ?30 ?20 ?10 120 snr/sfdr (dbfs/dbc) input amplitude (dbfs) sfdrfs sfdr snrfs snr 0 20 40 60 80 100 10215-026 figure 27. snr/sfdr vs. analog input level, f in = 9.7 mhz, f sample = 40 msps 105 20 30 25 40 35 snr/sfdr (dbfs/dbc) sample frequency (msps) 65 70 75 80 85 90 95 100 10215-027 sfdr snrfs figure 28. snr/sfdr vs. encode, f in = 19.7 mhz 105 70 ?40 85 snr/sfdr (dbfs/dbc) temperature (c) 75 80 85 90 95 100 ?15103560 sfdr (dbc) snr (dbfs) 10215-028 figure 29. snr/sfdr vs. temperature, f in = 9.7 mhz, f sample = 40 msps 110 100 0 0 200 snr/sfdr (dbfs/dbc) input frequency (mhz) 70 10 20 30 40 50 60 80 90 100 120 140 80 20 40 60 180 160 sfdr (dbc) snr (dbfs) 10215-029 figure 30. snr/sfdr vs. f in , f sample = 40 msps 20 30 25 40 35 105 snr/sfdr (dbfs/dbc) sample frequency (msps) 65 70 75 80 85 90 95 100 sfdr snrfs 10215-030 figure 31. snr/sfdr vs. encode, f in = 30.5 mhz 0 100,000 200,000 300,000 400,000 500,000 600,000 700,000 900,000 800,000 1,000,000 n ? 10 n ? 9 n ? 8 n ? 7 n ? 6 n ? 5 n ? 4 n ? 3 n ? 2 n ? 1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 number of hits output code 0.356 lsb rms 10215-031 figure 32. input-referred noise histogram, f sample = 40 msps
ad9637 data sheet rev. 0 | page 16 of 40 0 400 800 1600 1200 2000 2400 2800 3200 3600 4000 2.0 ?2.0 inl (lsb) output code ?1.6 ?1.2 ?0.8 ?0.4 0 0.4 0.8 1.2 1.6 10215-032 figure 33. inl, f in = 9.7 mhz, f sample = 40 msps 0 400 800 1600 1200 2000 2400 2800 3200 3600 4000 1.0 ?1.0 dnl (lsb) output code ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 10215-033 figure 34. dnl, f in = 9.7 mhz, f sample = 40 msps
data sheet ad9637 rev. 0 | page 17 of 40 equivalent circuits a v dd v in x 10215-034 figure 35. equivalent analog input circuit clk+ clk? 0.9v 15k ? 5 ? 5 ? 15k ? avdd a v dd 10215-035 figure 36. equivalent clock input circuit 30k ? 30k? sdio/dfs 350 ? a v dd 10215-036 figure 37. equivalent sdio/dfs input circuit dr v dd drgnd d? x d+ x v v v v 10215-037 figure 38. equivalent digital output circuit 350? a v dd 30k? sclk/dtp, sync, and pdwn 10215-038 figure 39. equivalent sclk/dtp , sync, and pdwn input circuit rbias a nd vcm 375 ? a v dd 10215-039 figure 40. equivalent rbias, vcm circuit csb 350? a v dd 30k? 10215-040 figure 41. equivalent csb input circuit vref a v dd 7.5k ? 375? 10215-041 figure 42. equivalent vref circuit
ad9637 data sheet rev. 0 | page 18 of 40 theory of operation the ad9637 is a multistage, pipelined adc. each stage provides sufficient overlap to correct for flash errors in the preceding stage. the quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. the serializer transmits this converted data in a 12-bit output. the pipelined architecture permits the first stage to operate with a new input sample, while the remaining stages operate with preceding samples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolution flash adc connected to a switched-capacitor dac and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (mdac)). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each stage to facilitate digital correction of flash errors. the last stage simply consists of a flash adc. the output staging block aligns the data, corrects errors, and passes the data to the output buffers. the data is then serialized and aligned to the frame and data clocks. analog input considerations the analog input to the ad9637 is a differential, switched capacitor circuit designed for processing differential input signals. this circuit can support a wide common-mode range while maintaining excellent performance. by using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. ss h c par c sample c sample c par v in? x h ss h v in+ x h 10215-042 figure 43. switched-cap acitor input circuit the clock signal alternately switches the input circuit between sample mode and hold mode (see figure 43 ). when the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. in addition, low q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, therefore, achieve the maximum bandwidth of the adc. such use of low q inductors or ferrite beads is required when driving the converter front end at high if frequencies. either a differential capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. this ultimately creates a low-pass filter at the input to limit unwanted broadband noise. see the an-742 application note, the an-827 application note , and the analog dialogue article transformer-coupled front-end for wideband a/d converters (volume 39, april 2005) for more information. in general, the precise values depend on the application. input common mode the analog inputs of the ad9637 are not internally dc-biased. therefore, in ac-coupled applications, the user must provide this bias externally. setting the device so that v cm = avdd/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in figure 44 . 100 20 0.5 snr/sfdr (dbfs/dbc) v cm (v) 30 40 50 60 70 80 90 0.7 0.9 1.1 1.3 snrfs sfdr 10215-043 figure 44. snr/sfdr vs. common-mode voltage, f in = 9.7 mhz, f sample = 80 msps an on-board, common-mode voltage reference is included in the design and is available from the vcm pin. the vcm pin must be decoupled to ground by a 0.1 f capacitor, as described in the applications information section. maximum snr performance is achieved by setting the adc to the largest span in a differential configuration. in the case of the ad9637 , the largest input span available is 2 v p-p.
data sheet ad9637 rev. 0 | page 19 of 40 differential input configurations there are several ways to drive the ad9637 either actively or passively. however, optimum performance is achieved by driving the analog input differentially. using a differential double balun configuration to drive the ad9637 provides excellent performance and a flexible interface to the adc (see figure 46 ) for baseband applications. for applications where snr is a key parameter, differential trans- former coupling is the recommended input configuration (see figure 47 ), because the noise performance of most amplifiers is not adequate to achieve the true performance of the ad9637. regardless of the configuration, the value of the shunt capacitor, c, is dependent on the input frequency and may need to be reduced or removed. it is not recommended to drive the ad9637 input single-ended. voltage reference a stable and accurate 1.0 v voltage reference is built into the ad9637 . vref can be configured using either the internal 1.0 v reference or an externally applied 1.0 v reference voltage. the various reference modes are summarized in the sections that follow. the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. internal reference connection a comparator within the ad9637 detects the potential at the sense pin and configures the reference into two possible modes, which are summarized in table 9 . if sense is grounded, the reference amplifier switch is connected to the internal resistor divider (see figure 45 ), setting vref to 1.0 v. table 9. reference configuration summary selected mode sense voltage (v) resulting v ref (v) resulting differential span (v p-p) fixed internal reference agnd to 0.2 1.0 internal 2.0 fixed external reference avdd 1.0 applied to external vref pin 2.0 vref sense 0.5v adc select logic 0.1f 1.0f vin? x vin+ x adc core 10215-044 figure 45. internal reference configuration adc r 0.1f 0.1f 2v p-p vcm c *c1 *c1 c r 0.1f 0.1f 0.1f 33? 200? 33? 33? 33? vin+ x vin? x et1-1-i3 c c 5pf r *c1 is optional 10215-045 figure 46. differential double balun input configuration for base band applications 2v p-p r r *c1 *c1 is optional 49.9 ? 0.1 f a dt1-1wt 1:1 z ratio vin? x adc vin+ x *c1 c vcm 33? 33? 200 ? 0.1f 5pf 10215-046 figure 47. differential transformer-coupled configuration for baseband applications
ad9637 data sheet rev. 0 | page 20 of 40 3 . 0 if the internal reference of the ad9637 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. figure 48 shows how the internal reference voltage is affected by loading. 0 ?0.5 ?1.0 ?1.5 ?2.0 ?2.5 ?3.0 ?3.5 ?4.0 ?4.5 ?5.0 0 2.5 2.0 1.5 1.0 0.5 v ref error (%) load current (ma) internal v ref = 1v 10215-047 figure 48. v ref error vs. load current external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the adc or improve thermal drift charac- teristics. figure 49 shows the typical drift characteristics of the internal reference in 1.0 v mode. 10215-048 4 ?8 ?40 85 v ref error (mv) temperature (c) ?6 ?4 ?2 0 2 ?15 10 35 60 figure 49. typical v ref drift when the sense pin is tied to avdd, the internal reference is disabled, allowing the use of an external reference. an internal reference buffer loads the external reference with an equivalent 7.5 k load (see figure 42 ). the internal buffer generates the positive and negative full-scale references for the adc core. therefore, the external reference must be limited to a maximum of 1.0 v. it is not recommended to leave the sense pin floating. clock input considerations for optimum performance, clock the ad9637 sample clock inputs, clk+ and clk?, with a differential signal. the signal is typically ac-coupled into the clk+ and clk? pins via a transformer or capacitors. these pins are biased internally (see figure 36 ) and require no external bias. clock input options the ad9637 has a very flexible clock input structure. the clock input can be a cmos, lvds, lvpecl, or sine wave signal. regardless of the type of signal being used, clock source jitter is of the utmost concern, as described in the jitter considerations section. figure 50 and figure 51 show two preferred methods for clocking the ad9637 (at clock rates of up to 640 mhz prior to the internal clk divider). a low jitter clock source is converted from a single- ended signal to a differential signal using either an rf transformer or an rf balun. the rf balun configuration is recommended for clock frequencies between 80 mhz and 640 mhz, and the rf transformer is recom- mended for clock frequencies from 10 mhz to 200 mhz. the back-to-back schottky diodes across the transformer/balun secondary winding limit clock excursions into the ad9637 to approximately 0.8 v p-p differential. this limit helps prevent the large voltage swings of the clock from feeding through to other portions of the ad9637 while preserving the fast rise and fall times of the signal that are critical to a low jitter performance. however, the diode capacitance comes into play at frequencies above 500 mhz. care must be taken in choosing the appropriate signal limiting diode. 0.1f 0.1f 0.1f 0.1f schottky diodes: hsms2822 clock input 50? 100 ? clk? clk+ adc mini-circuits ? adt1-1wt, 1:1 z xfmr 10215-049 figure 50. transformer coupled differential clock (up to 200 mhz) 0.1f 0.1f 0.1f clock input 0.1f 50 ? clk? clk+ schottky diodes: hsms2822 adc 10215-050 figure 51. balun coupled differential clock (80 mhz to 640 mhz)
data sheet ad9637 rev. 0 | page 21 of 40 if a low jitter clock source is not available, another option is to ac couple a differential pecl signal to the sample clock input pins, as shown in figure 52 . the ad9510/ ad9511 / ad9512 / ad9513/ ad9514 / ad9515 / ad9516/ ad9517 clock drivers offer excellent jitter performance. causes the clock divider to reset to its initial state. this synchronization feature allows multiple parts to have their clock dividers aligned to guarantee simultaneous input sampling. clock duty cycle typical high speed adcs use both clock edges to generate a variety of internal timing signals and, as a result, may be sensitive to clock duty cycle. commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. a third option is to ac couple a differential lvds signal to the sample clock input pins, as shown in figure 53 . the ad9510 / ad9511/ ad9512 / ad9513 / ad9514/ ad9515 / ad9516/ ad9517 clock drivers offer excellent jitter performance. the ad9637 contains a duty cycle stabilizer (dcs) that retimes the nonsampling (falling) edge, providing an internal clock signal with a nominal 50% duty cycle. this allows the user to provide a wide range of clock input duty cycles without affecting the performance of the ad9637 . noise and distortion performance are nearly flat for a wide range of duty cycles with the dcs turned on. in some applications, it may be acceptable to drive the sample clock inputs with a single-ended 1.8 v cmos signal. in such applications, drive the clk+ pin directly from a cmos gate, and bypass the clk? pin to ground with a 0.1 f capacitor (see figure 54 ). input clock divider the ad9637 contains an input clock divider with the ability to divide the input clock by integer values between 1 and 8. jitter in the rising edge of the input is still of concern and is not easily reduced by the internal stabilization circuit. the duty cycle control loop does not function for clock rates less than 20 mhz, nominally. the loop has a time constant associated with it that must be considered in applications in which the clock rate can change dynamically. a wait time of 1.5 s to 5 s is required after a dynamic clock frequency increase or decrease before the dcs loop is relocked to the input signal. the ad9637 clock divider can be synchronized using the external sync input. bit 0 and bit 1 of register 0x109 allow the clock divider to be resynchronized on every sync signal or only on the first sync signal after the register is written. a valid sync 100 ? 0.1f 0.1f 0.1f 0.1f 240 ? 240? 50k? 50k ? clk? clk+ clock input clock input adc ad951x pecl driver 10215-051 figure 52. differential pecl sample clock (up to 640 mhz) 100 ? 0.1f 0.1f 0.1f 0.1f 50k? 50k ? clk? clk+ adc clock input clock input ad951x lvds driver 10215-052 figure 53. differential lvds sample clock (up to 640 mhz) optional 100 ? 0.1f 0.1f 0.1f 50? 1 1 50 ? resistor is optional. clk? clk+ adc v cc 1k ? 1k ? c lock input ad951x cmos driver 10215-053 figure 54. single-ended 1.8 v cm os input clock (up to 200 mhz)
ad9637 data sheet rev. 0 | page 22 of 40 jitter considerations high speed, high resolution adcs are sensitive to the quality of the clock input. the degradation in snr at a given input frequency (f a ) due only to aperture jitter (t j ) can be calculated by snr degradation = 20 log 10 ? ? ? ? ? ? ? ? ja tf 2 1 in this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and adc aperture jitter specifications. if undersampling applications are particularly sensitive to jitter (see figure 55 ). the clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the ad9637 . power supplies for clock drivers should be separated from the adc output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step. refer to the an-501 application note and the an-756 application note for more in-depth information about jitter performance as it relates to adcs. 1 10 100 1000 16 bits 14 bits 12 bits 30 40 50 60 70 80 90 100 110 120 130 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps analog input frequency (mhz) 10 bits 8 bits rms clock jitter requirement snr (db) 10215-054 figure 55. ideal snr vs. input frequency and jitter power dissipation an d power-down mode as shown in figure 56 , the power dissipated by the ad9637 is proportional to its sample rate. the digital power dissipation does not vary significantly because it is determined primarily by the drvdd supply and bias current of the lvds output drivers. 10215-055 400 300 350 250 200 150 10 analog power (mw) sample rate (msps) 20 30 40 50 60 70 80 65msps 80msps 50msps 40msps 20msps figure 56. analog core power vs. f sample for f in = 9.7 mhz the ad9637 is placed in power-down mode either by the spi port or by asserting the pdwn pin high. in this state, the adc typically dissipates 1 mw. during power-down, the output drivers are placed in a high impedance state. asserting the pdwn pin low returns the ad9637 to its normal operating mode. note that pdwn is referenced to the digital output driver supply (drvdd) and should not exceed that supply voltage. low power dissipation in power-down mode is achieved by shutting down the reference, reference buffer, biasing networks, and clock. internal capacitors are discharged when entering power-down mode and then must be recharged when returning to normal operation. as a result, wake-up time is related to the time spent in power-down mode, and shorter power-down cycles result in proportionally shorter wake-up times. when using the spi port interface, the user can place the adc in power-down mode or standby mode. standby mode allows the user to keep the internal reference circuitry powered when faster wake-up times are required. see the memory map section for more details on using these features.
data sheet ad9637 rev. 0 | page 23 of 40 10215-056 fco 500mv/div dco 500mv/div data 500mv/div 5ns/div digital outputs and timing the ad9637 differential outputs conform to the ansi-644 lvds standard on default power-up. this can be changed to a low power, reduced signal option (similar to the ieee 1596.3 standard) via the spi. the lvds driver current is derived on chip and sets the output current at each output equal to a nominal 3.5 ma. a 100 differential termination resistor placed at the lvds receiver inputs results in a nominal 350 mv swing (or 700 mv p-p differential) at the receiver. when operating in reduced range mode, the output current is reduced to 2 ma. this results in a 200 mv swing (or 400 mv p-p differential) across a 100 termination at the receiver. the ad9637 lvds outputs facilitate interfacing with lvds receivers in custom asics and fpgas for superior switching performance in noisy environments. single point-to-point net topologies are recommended with a 100 termination resistor placed as close to the receiver as possible. if there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. to avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. an example of the fco and data stream with proper trace length and position is shown in figure 57 . an example of lvds output timing in reduced range mode is shown in figure 58 . figure 57. lvds output timing example in ansi-644 mode (default) 10215-057 fco 500mv/div dco 500mv/div data 500mv/div 5ns/div figure 58. lvds output timing example in reduced range mode
ad9637 data sheet rev. 0 | page 24 of 40 figure 59 shows an example of the lvds output using the ansi-644 standard (default) data eye and a time interval error (tie) jitter histogram with trace lengths of less than 24 inches on standard fr-4 material. 10215-058 0.5k 1.0k 1.5k 3.0k 2.5k 2.0k 0 ? 60ps ? 40ps ? 20ps 0ps 20ps 40ps 60ps 80ps tie jitter histogram (hits) 300 200 100 ?300 ?200 ?100 0 ?0.8ns 0.8ns ?0.6ns 0.6ns ?0.4ns 0.4ns ?0.2ns 0.2ns 0ns eye diagram voltage (mv) eye: all bits uls: 8000:448000 figure 59. data eye for lvds outputs in ansi-644 mode with trace lengths of less than 24 inches on standard fr-4, external 100 far-end termination only figure 60 shows an example of trace lengths exceeding 24 inches on standard fr-4 material. note that the tie jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. it is the responsibility of the user to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. additional spi options allow the user to further increase the internal termination (increasing the current) of all eight outputs to drive longer trace lengths, which can be achieved by program- ming register 0x15. even though this option produces sharper rise and fall times on the data edges and is less prone to bit errors, it also increases the power dissipation of the drvdd supply. 10215-059 0.5k 1.0k 1.5k 3.0k 2.5k 2.0k 0 ? 60ps ? 40ps ? 20ps 0ps 20ps 40ps 60ps 80ps tie jitter histogram (hits) 300 200 100 ?300 ?200 ?100 0 ?0.8ns 0.8ns ?0.6ns 0.6ns ?0.4ns 0.4ns ?0.2ns 0.2ns 0ns eye diagram voltage (mv) eye: all bits uls: 7000:448000 figure 60. data eye for lvds outputs in ansi-644 mode with trace lengths greater than 24 inches on standard fr-4, external 100 far termination only the default format of the output data is twos complement. table 1 0 shows an example of the output coding format. to change the output data format to offset binary, see the memory map section. data from each adc is serialized and provided on a separate channel in ddr mode. the data rate for each serial stream is equal to 12 bits times the sample clock rate, quantity divided by 2, with a maximum of 480 mbps (12 bits 80 msps)/2 = 480 mbps. the lowest typical conversion rate is 10 msps. see the memory map section for details on enabling this feature. table 10. digital output coding input (v) condition (v) offset binary output mode twos complement mode vin+ ? vin? < ?vref ? 0.5 lsb 0000 0000 0000 1000 0000 0000 vin+ ? vin? = ?vref 0000 0000 0000 1000 0000 0000 vin+ ? vin? = 0 1000 0000 0000 0000 0000 0000 vin+ ? vin? = +vref ? 1.0 lsb 1111 1111 1111 0111 1111 1111 vin+ ? vin? > +vref ? 0.5 lsb 1111 1111 1111 0111 1111 1111
data sheet ad9637 rev. 0 | page 25 of 40 two output clocks are provided to assist in capturing data from the ad9637 . the dco is used to clock the output data and is equal to 6 the sample clock (clk) rate for the default mode of opera- tion. data is clocked out of the ad9637 and must be captured on the rising and falling edges of the dco that supports double data rate (ddr) capturing. the fco is used to signal the start of a new output byte and is equal to the sample clock rate (see the timing diagrams section). when the spi is used, the dco phase can be adjusted in 60 increments relative to the data edge. this enables the user to refine system timing margins, if required. the default dco+ and dco? timing, as shown in figure 2 , is 90 relative to the output data edge. a 10-bit serial stream can also be initiated from the spi. this allows the user to implement and test compatibility to lower resolution systems. when changing the resolution to a 10-bit serial stream, the data stream is shortened. see figure 3 for the 10-bit example. in default mode, as shown in figure 2 , the msb is first in the data output serial stream. this can be inverted so that the lsb is first in the data output serial stream by using the spi. there are 12 digital output test pattern options available that can be initiated through the spi. this is a useful feature when validating receiver capture and timing (see table 11 for the output bit sequencing options that are available). some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. note that some patterns do not adhere to the data format select option. in addition, custom user-defined test patterns can be assigned in the 0x19, 0x1a, 0x1b, and 0x1c register addresses. table 11. flexible output test modes output test mode bit sequence pattern name digital output word 1 digital output word 2 subject to data format select notes 0000 off (default) n/a n/a n/a 0001 midscale short 1000 0000 0000 (12-bit) n/a yes offset binary code shown 10 0000 0000 (10-bit) n/a yes offset binary code shown 0010 +full-scale short 1111 1111 1111 (12-bit) n/a yes offset binary code shown 11 1111 1111 (10-bit) n/a yes offset binary code shown 0011 ?full-scale short 0000 0000 0000 (12-bit) n/a yes offset binary code shown 00 0000 0000 (10-bit) n/a yes offset binary code shown 0100 checkerboard 1010 1010 1010 (12-bit) 0101 0101 0101 (12-bit) no 10 1010 1010 (10-bit) 01 0101 0101 (10-bit) no 0101 pn sequence long 1 n/a n/a yes pn23 itu 0.150 x 23 + x 18 + 1 0110 pn sequence short 1 n/a n/a yes pn9 itu o.150 x 9 + x 5 + 1 0111 one-/zero-word toggle 1111 1111 1111 (12-bit) 0000 0000 0000 (12-bit) no 11 1111 1111 (10-bit) 00 0000 0000 (10-bit) no 1000 user input reg. 0x19 to reg. 0x1a reg. 0x1b to reg. 0x1c no 1001 1-/0-bit toggle 1010 1010 1010 (12-bit) n/a no 10 1010 1010 (10-bit) n/a no 1010 1 sync 0000 0011 1111 (12-bit) n/a no 00 0001 1111 (10-bit) n/a no 1011 one bit high 1000 0000 0000 (12-bit) n/a no pattern associated with the external pin 10 0000 0000 (10-bit) n/a no pattern associated with the external pin 1100 mixed frequency 1010 0011 0011 (12-bit) n/a no 10 0110 0011 (10-bit) n/a no 1 all test mode options except pn sequence short and pn sequence long can support 10-bit to 12-bit word lengths to verify data c apture to the receiver.
ad9637 data sheet rev. 0 | page 26 of 40 the pn sequence short pattern produces a pseudorandom bit sequence that repeats itself every 2 9 ? 1 or 511 bits. a description of the pn sequence and how it is generated can be found in section 5.1 of the itu-t 0.150 (05/96) standard. the seed value is all 1s (see tabl e 12 for the initial values). the output is a parallel representation of the serial pn9 sequence in msb first format. the first output word is the first 12 bits of the pn9 sequence in msb aligned format. table 12. pn sequence sequence initial value first three output samples (msb first) twos complement pn sequence short 0x1fe0 0x1df1, 0x3cc8, 0x294e pn sequence long 0x1fff 0x1fe0, 0x2001, 0x1c00 the pn sequence long pattern produces a pseudorandom bit sequence that repeats itself every 2 23 ? 1 or 8,388,607 bits. a description of the pn sequence and how it is generated can be found in section 5.6 of the itu-t 0.150 (05/96) standard. the seed value is all 1s (see table 12 for the initial values) and the ad9637 inverts the bit stream with relation to the itu standard. the output is a parallel representation of the serial pn23 sequence in msb first format. the first output word is the first 12 bits of the pn23 sequence in msb aligned format. see the memory map section for information on how to change these additional digital output timing features through the spi. sdio/dfs pin for applications that do not require spi mode operation, the csb pin is tied to avdd, and the sdio/dfs pin controls the output data format select operation according to tabl e 13 . table 13. output data format select pin settings dfs pin voltage output mode avdd twos complement gnd (default) offset binary sclk/dtp pin the sclk/dtp pin is for use in applications that do not require spi mode operation. this pin can enable a single digital test pattern if it and the csb pin are both held high during device power-up. when sclk/dtp is tied to avdd, the adc channel outputs shift out the following pattern: 1000 0000 0000. the fco and dco function normally while all channels shift out the repeatable test pattern. this pattern allows the user to perform timing alignment adjustments among the fco, dco, and output data. this pin has an internal 30 k resistor to gnd. it can be left unconnected for normal operation. table 14. digital test pattern pin settings selected dtp dtp voltage resulting d x normal operation no connect normal operation dtp avdd 1000 0000 0000 additional and custom test patterns can also be observed when commanded from the spi port. consult the memory map section for information about the options available. csb pin the csb pin should be tied to avdd for applications that do not require spi mode operation. tying csb high causes all sclk and sdio information to be ignored. rbias pin to set the internal core bias current of the adc, place a 10.0 k, 1% tolerance resistor to ground at the rbias pin.
data sheet ad9637 rev. 0 | page 27 of 40 built-in output test modes the ad9637 includes a built-in test feature designed to enable verification of the integrity of each data output channel, as well as to facilitate board level debugging. various output test options are provided to place predictable values on the outputs of the ad9637. output test modes the output test options are described in table 17 at address 0x0d. when an output test mode is enabled, the analog section of the adc is disconnected from the digital back-end blocks and the test pattern is run through the output formatting block. some of the test patterns are subject to output formatting, and some are not. the pn generators from the pn sequence tests can be reset by setting bit 4 or bit 5 of register 0x0d. these tests can be performed with or without an analog signal (if present, the analog signal is ignored), but they do require an encode clock. for more information, see the an-877 application note, interfacing to high speed adcs via spi .
ad9637 data sheet rev. 0 | page 28 of 40 serial port interface (spi) the ad9637 serial port interface (spi) allows the user to configure the converter for specific functions or operations through a structured register space provided inside the adc. the spi gives the user added flexibility and customization, depending on the application. addresses are accessed via the serial port and can be written to or read from via the port. memory is organized into bytes that can be further divided into fields, which are docu- mented in the memory map section. for detailed operational information, see the an-877 application note , interfacing to high speed adcs via spi . configuration using the spi three pins define the spi of this adc: the sclk/dtp pin, the sdio/dfs pin, and the csb pin (see table 15 ). the sclk (a serial clock) is used to synchronize the read and write data presented from and to the adc. the sdio (serial data input/ output) is a dual-purpose pin that allows data to be sent to and read from the internal adc memory map registers. the csb (chip select bar) is an active low control that enables or disables the read and write cycles. table 15. serial port interface pins pin function sclk serial clock. the serial shift clock input, which is used to synchronize serial interface reads and writes. sdio serial data inp ut/output. a dual-purpose pin that typically serves as an input or an output, depending on the instruction being sent and the relative position in the timing frame. csb chip select bar. an active low control that gates the read and write cycles. the falling edge of the csb, in conjunction with the rising edge of the sclk, determines the start of the framing. an example of the serial timing and its definitions can be found in figure 61 and table 5 . other modes involving the csb are available. the csb can be held low indefinitely, which permanently enables the device; this is called streaming. the csb can stall high between bytes to allow for additional external timing. when csb is tied high, spi functions are placed in high impedance mode. this mode turns on any spi pin secondary functions. during an instruction phase, a 16-bit instruction is transmitted. data follows the instruction phase, and its length is determined by the w0 and w1 bits. in addition to word length, the instruction phase determines whether the serial frame is a read or write operation, allowing the serial port to be used both to program the chip and to read the contents of the on-chip memory. the first bit of the first byte in a multibyte serial data transfer frame indicates whether a read command or a write command is issued. if the instruction is a readback operation, performing a readback causes the serial data input/output (sdio) pin to change direction from an input to an output at the appropriate point in the serial frame. all data is composed of 8-bit words. data can be sent in msb first mode or in lsb first mode. msb first is the default on power-up and can be changed via the spi port configuration register. for more information about this and other features, see the an-877 application note , interfacing to high speed adcs via spi . don?t care don?t care don?t care don?t care sdio sclk csb t s t dh t clk t ds t h r/w w1 w0 a12 a11 a10 a9 a8 a7 d5 d4 d3 d2 d1 d0 t low t high 10215-060 figure 61. serial port interface timing diagram
data sheet ad9637 rev. 0 | page 29 of 40 hardware interface the pins described in table 15 comprise the physical interface between the user programming device and the serial port of the ad9637 . the sclk pin and the csb pin function as inputs when using the spi interface. the sdio pin is bidirectional, functioning as an input during write phases and as an output during readback. the spi interface is flexible enough to be controlled by either fpgas or microcontrollers. one method for spi configuration is described in detail in the an-812 application note , micro- controller-based serial port interface (spi) boot circuit . the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk signal, the csb signal, and the sdio signal are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9637 to prevent these signals from transi- tioning at the converter inputs during critical sampling periods. some pins serve a dual function when the spi interface is not being used. when the pins are strapped to drvdd or ground during device power-on, they are associated with a specific function. tabl e 16 describes the strappable functions supported on the ad9637. configuration without the spi in applications that do not interface to the spi control registers, the sdio/dfs pin, the sclk/dtp pin, and the pdwn pin serve as standalone cmos-compatible control pins. when the device is powered up, it is assumed that the user intends to use the pins as static control lines for the output data format, output digital test pattern, and power-down feature control. in this mode, csb should be connected to avdd, which disables the serial port interface. when the device is in spi mode, the pdwn pin (if enabled) remains active. for spi control of power-down, the pdwn pin should be set to its default state. spi accessible features table 16 provides a brief description of the general features that are accessible via the spi. these features are described in detail in the an-877 application note , interfacing to high speed adcs via spi . the ad9637 part-specific features are described in detail in the memory map register descriptions section following table 17 , the external memory map register table. table 16. features accessible using the spi feature name description mode allows the user to set either power-down mode or standby mode clock allows the user to access the dcs, set the clock divider, set the clock divider phase, and enable the sync offset allows the user to digitally adjust the converter offset test i/o allows the user to set test modes to have known data on output bits output mode allows the user to set the output mode output phase allows the user to set the output clock polarity adc resolution and speed grade scalable power consumption options based on resolution and speed grade selection
ad9637 data sheet rev. 0 | page 30 of 40 memory map reading the memory map register table each row in the memory map register table has eight bit locations. the memory map is roughly divided into three sections: the chip configuration registers (address 0x00 to address 0x02); the device index and transfer registers (address 0x05 and address 0xff) and the global adc functions registers, including setup, control, and test (address 0x08 to address 0x109). the memory map register table (see table 17 ) lists the default hexadecimal value for each hexadecimal address shown. the column with the heading bit 7 (msb) is the start of the default hexadecimal value given. for example, address 0x05, the device index register, has a hexadecimal default value of 0x3f. this means that in address 0x05, bits[7:6] = 0, and the remaining bits[5:0] = 1. this setting is the default channel index setting. the default value results in both adc channels receiving the next write command. for more information on this function and others, see the an-877 application note, interfacing to high speed adcs via spi. this application note details the functions controlled by register 0x00 to register 0xff. the remaining registers are documented in the memory map register descriptions section. open locations all address and bit locations that are not included in table 17 are not currently supported for this device. unused bits of a valid address location should be written with 0s. writing to these locations is required only when part of an address location is open (for example, address 0x05). if the entire address location is open or not listed in table 17 (for example, address 0x13) this address location should not be written. default values after the ad9637 is reset, critical registers are loaded with default values. the default values for the registers are given in table 17 , the memory map register table. logic levels an explanation of logic level terminology follows: ? bit is set is synonymous with bit is set to logic 1 or writing logic 1 for the bit. ? clear a bit is synonymous with bit is set to logic 0 or writing logic 0 for the bit. channel-specific registers some channel setup functions, such as the signal monitor thresholds, can be programmed differently for each channel. in these cases, channel address locations are internally duplicated for each channel. these registers and bits are designated in table 17 as local. these local registers and bits can be accessed by setting the appropriate data channel bits (a, b, c, or d) and the clock channel dco/fco bits (bits[5:4]) in register 0x05. if all the bits are set, the subsequent write affects the registers of all channels and the dco/fco clock channels. in a read cycle, only one of the channels, a, b, c, or d, should be set to read one of the four registers. if all the bits are set during a spi read cycle, the part returns the value for channel a. registers and bits designated as global in tabl e 17 affect the entire part or the channel features for which independent settings are not allowed between channels. the settings in register 0x05 do not affect the global registers and bits.
data sheet ad9637 rev. 0 | page 31 of 40 memory map register table the ad9637 uses a 3-wire interface and 16-bit addressing and, therefore, bit 0 and bit 7 in register 0x00 are set to 0, and bit 3 and bit 4 are set to 1. when register 0x00, bit 5 is set high, the spi enters a soft reset, where all of the user registers revert to their default values and bit 2 is automatically cleared. table 17. memory map register table reg. addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments chip configurati on registers 0x00 spi port configuration 0 = sdo active lsb first soft reset 1 = 16-bit address 1 = 16-bit address soft reset lsb first 0 = sdo active 0x18 the nibbles are mirrored so that lsb or msb first mode registers correctly. the default for the adcs is 16-bit mode. 0x01 chip id (global) 8-bit chip id, bits[7:0] ad9637 0x93 = octal 12-bit 40 ms ps/80 msps serial lvds read only 0x93 unique chip id that is used to differentiate devices; read only. 0x02 chip grade (global) open speed grade id, bits[6:4] 001 = 40 msps 100 = 80 msps open open open open read only unique speed grade id that is used to differentiate graded devices; read only. device index and transfer registers 0x04 device index 2 open open open open data channel h data channel g data channel f data channel e 0xf bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0x05 device index 1 open open clock channel dco clock channel fco data channel d data channel c data channel b data channel a 0x3f bits are set to determine which device on chip receives the next write command. the default is all devices on chip. 0xff transfer open open open open open open open initiate override 0x00 set resolution/ sample rate override. global adc functions 0x08 power modes (global) open open external power- down pin function 0 = full power- down 1 = standby open open open internal power-down mode 00 = chip run 01 = full power-down 10 = standby 11 = reset 0x00 determines various generic modes of chip operation. 0x09 clock (global) open ope n open open ope n open open duty cycle stabilizer 0 = off 1 = on 0x01 turns duty cycle stabilizer on or off.
ad9637 data sheet rev. 0 | page 32 of 40 reg. addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x0b clock divide (global) open open open open open clock divide ratio, bits[2:0] 000 = divide by 1 001 = divide by 2 010 = divide by 3 011 = divide by 4 100 = divide by 5 101 = divide by 6 110 = divide by 7 111 = divide by 8 0x00 the divide ratio is the value plus 1. 0x0c enhancement control open open open open open chop mode 0 = off 1 = on open open 0x00 enables/ disables chop mode. 0x0d test mode (local except for pn sequence resets) user input test mode 00 = single 01 = alternate 10 = single once 11 = alternate once (affects user input test mode only, bits[3:0] = 1000) reset pn long gen reset pn short gen output test mode, bits[3:0] (local) 0000 = off (default) 0001 = midscale short 0010 = positive fs 0011 = negative fs 0100 = alternating checkerboard 0101 = pn 23 sequence 0110 = pn 9 sequence 0111 = one/zero word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1 sync 1011 = one bit high 1100 = mixed bit frequency 0x00 when set, the test data is placed on the output pins in place of normal data. 0x10 offset adjust (local) 8-bit device offset adjustment, bits[7:0] (local) offset adjust in lsbs from +127 to ?128 (twos complement format) 0x00 device offset trim. 0x14 output mode open lvds-ansi/ lvds-ieee option 0 = lvds- ansi 1 = lvds- ieee reduced range link (global) (see table 18 ) open open open output invert (local) open output format 0 = offset binary 1 = twos comple- ment (global) 0x01 configures the outputs and the format of the data. 0x15 output adjust open open output driver termination, bits[1:0] 00 = none 01 = 200 10 = 100 11 = 100 open open open output drive 0 = 1 drive 1 = 2 drive 0x00 determines lvds or other output properties. 0x16 output phase open input cl ock phase adjust, bits[6:4] (value is number of input clock cycles of phase delay) (see table 19) output clock phase adjust, bits[3:0] (setting = 0000 through 1011) (see table 20) 0x03 on devices that use global clock divide, determines which phase of the divider output is used to supply the output clock. internal latching is unaffected. 0x18 v ref open open open open open internal v ref adjustment digital scheme, bits[2:0] 000 = 1.0 v p-p 001 = 1.14 v p-p 010 = 1.33 v p-p 011 = 1.6 v p-p 100 = 2.0 v p-p 0x04 selects and/or adjusts the v ref .
data sheet ad9637 rev. 0 | page 33 of 40 reg. addr. (hex) parameter name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value (hex) comments 0x19 user_patt1_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 1 lsb. 0x1a user_patt1_ms b (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 1 msb. 0x1b user_patt2_lsb (global) b7 b6 b5 b4 b3 b2 b1 b0 0x00 user defined pattern 2 lsb. 0x1c user_patt2_ms b (global) b15 b14 b13 b12 b11 b10 b9 b8 0x00 user defined pattern 2 msb. 0x21 serial control (global) lvds output lsb first word-wise ddr 1-lane, bits[6:4] 100 = ddr 1-lane open open serial output number of bits 10 = 12 bits 11 = 10 bits 0x42 serial stream control. default causes msb first and the native bit stream. 0x22 serial channel status (local) open open open open open open channel output reset channel power- down 0x00 used to power down individual sections of a converter. 0x100 resolution/ sample rate override open resolution/ sample rate override enable resolution 10 = 12 bits 11 = 10 bits open sample rate 000 = 20 msps 001 = 40 msps 010 = 50 msps 011 = 65 msps 100 = 80 msps 0x00 resolution/ sample rate override (requires transfer bit, 0xff). 0x101 user i/o control 2 ope n open open open open open open sdio pull-down 0x00 disables sdio pull-down. 0x102 user i/o control 3 open open open open vcm power- down open open open 0x 00 vcm control. 0x109 sync open open open open open open sync next only enable sync 0x00
ad9637 data sheet rev. 0 | page 34 of 40 memory map register descriptions for additional information about functions controlled in register 0x00 to register 0xff, see the an-877 application note , interfacing to high speed adcs via spi . device index (register 0x04 and register 0x05) there are certain features in the map that can be set independently for each channel, whereas other features apply globally to all channels (depending on context), regardless of which are selected. the first four bits in register 0x04 and register 0x05 can be used to select which individual data channels are affected. the output clock channels can be selected in register 0x05, as well. a smaller subset of the independent feature list can be applied to those devices. transfer (register 0xff) all registers except register 0x100 are updated the moment they are written. setting bit 0 of this transfer register high initializes the settings in the adc sample rate override register (address 0x100). power modes (register 0x08) bits6open bit 5external power-down pin function if set, the external pdwn pin initiates standby mode. if cleared, the external pdwn pin initiates power-down mode. bits[4:2]open bits[1:0]internal power-down mode in normal operation (bits[1:0] = 00), all adc channels are active. in power-down mode (bits[1:0] = 01), the digital data path clocks are disabled while the digital data path is reset. outputs are disabled. in standby mode (bits[1:0] = 10), the digital data path clocks and the outputs are disabled. during a digital reset (bits[1:0] = 11), all the digital data path clocks and the outputs (where applicable) on the chip are reset, except the spi port. note that the spi is always left under control of the user, that is, it is never automatically disabled or in reset (except by power-on reset). enhancement control (register 0x0c) bits3open bit 2chop mode for applications that are sensitive to offset voltages and other low frequency noise, such as homodyne or direct conversion receivers, chopping in the first stage of the ad9637 is a feature that can be enabled by setting bit 2. in the frequency domain, chopping translates offsets and other low frequency noise to f clk /2, where they can be filtered. bits[1:0]open output mode (register 0x14) bit open bit 6lvds-asi/lvds-ieee option setting this bit chooses the lvds-ieee (reduced range) option. the default setting is lvds-ansi. as described in table 18 , w hen lvds-ansi or lvds-ieee reduced range link is s ele c te d, the user can select the driver termination. the driver current is automatically selected to give the proper output swing. table 18. lvds-ansi/lvds-ieee options output mode, bit[6] output mode output driver termination output driver current 0 lvds-ansi user selectable automatically selected to give proper swing 1 lvds-ieee reduced range link user selectable automatically selected to give proper swing bits[5:3]open bit 2output invert setting this bit inverts the output bit stream. bit 1open bit 0output format by default, this bit is set to send the data output in twos complement format. resetting this bit changes the output mode to offset binary. output adjust (register 0x15) bits6open bits54output driver termination these bits allow the user to select the internal termination resistor. bits[3:1]open bit 0output drive bit 0 of the output adjust register controls the drive strength on the lvds driver of the fco and dco outputs only. the default values set the drive to 1. the drive can be increased to 2 by setting the appropriate channel bit in register 0x05 and then setting bit 0. these features cannot be used with the output driver termination select. the termination selection takes precedence over the 2 driver strength on fco and dco when both the output driver termination and output drive are selected.
data sheet ad9637 rev. 0 | page 35 of 40 output phase (register 0x16) bit 7open bits[6:4]input clock phase adjust table 19. input clock phase adjust options input clock phase adjust, bits[6:4] number of input clock cycles of phase delay 000 (default) 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 bits[3:0]output clock phase adjust table 20. output clock phase adjust options output clock (dco), phase adjust, bits[3:0] dco phase adjustment (degrees relative to d x edge) 0000 0 0001 60 0010 120 0011 (default) 180 0100 240 0101 300 0110 360 0111 420 1000 480 1001 540 1010 600 1011 660 resolution/sample rate ov erride (register 0x100) this register is designed to allow the user to downgrade the device. any attempt to upgrade the default speed grade results in a chip power-down. settings in this register are not initialized until bit 0 of the transfer register (register 0xff) is written high. user i/o control 2 (register 0x101) bits[7:1]open bit 0sdio pull-down bit 0 can be set to disable the internal 30 k pull-down on the sdio pin, which can be used to limit loading when many devices are connected to the spi bus. user i/o control 3 (register 0x102) bits[7:4]open bit 3vcm power-down bit 3 can be set high to power down the internal vcm generator. this feature is used when applying an external reference. bits[2:0]open
ad9637 data sheet rev. 0 | page 36 of 40 applications information design guidelines before starting the design and layout of the ad9637 as a system, it is recommended that the designer become familiar with these guidelines, which describes the special circuit connections and layout requirements that are needed for certain pins. power and ground recommendations when connecting power to the ad9637 , it is recommended that two separate 1.8 v supplies be used. use one supply for analog (avdd); use a separate supply for the digital outputs (drvdd). for both avdd and drvdd, several different decoupling capacitors should be used to cover both high and low frequencies. place these capacitors close to the point of entry at the pcb level and close to the pins of the part, with minimal trace length. a single pcb ground plane should be sufficient when using the ad9637 . with proper decoupling and smart partitioning of the pcb analog, digital, and clock sections, optimum performance is easily achieved. exposed pad thermal heat slug recommendations it is required that the exposed pad on the underside of the adc be connected to analog ground (agnd) to achieve the best electrical and thermal performance of the ad9637. an exposed continuous copper plane on the pcb should mate to the ad9637 exposed pad, pin 0. the copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the pcb. these vias should be solder-filled or plugged. to maximize the coverage and adhesion between the adc and pcb, partition the continuous copper plane by overlaying a silk- screen on the pcb into several uniform sections. this provides several tie points between the adc and pcb during the reflow process, whereas using one continuous plane with no partitions guarantees only one tie point. for detailed information on packaging and the pcb layout of chip scale packages, see the an-772 application note, a design and manufacturing guide for the lead frame chip scale package (lfcsp) , at www.analog.com . vcm the vcm pin should be decoupled to ground with a 0.1 f capacitor. reference decoupling the vref pin should be externally decoupled to ground with a low esr, 1.0 f capacitor in parallel with a low esr, 0.1 f ceramic capacitor. spi port the spi port should not be active during periods when the full dynamic performance of the converter is required. because the sclk, csb, and sdio signals are typically asynchronous to the adc clock, noise from these signals can degrade converter performance. if the on-board spi bus is used for other devices, it may be necessary to provide buffers between this bus and the ad9637 to keep these signals from transitioning at the con- verter inputs during critical sampling periods.
data sheet ad9637 rev. 0 | page 37 of 40 outline dimensions compliant to jedec standards mo-220-vmmd-4 091707-c 6.35 6.20 sq 6.05 0.25 min top view 8.75 bsc sq 9.00 bsc sq 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 7.50 ref 0.05 max 0.02 nom 0.60 max 0.60 max exposed pad (bottom view) seating plane pin 1 indicator pin 1 indicator 0.30 0.23 0.18 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 62. 64-lead lead frame chip scale package [lfcsp_vq] 9 mm 9 mm body, very thin quad (cp-64-4) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad9637bcpz-40 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 ad9637bcpzrl7-40 ?40c to +85c 64-lead lead fr ame chip scale package [lfcsp_vq] cp-64-4 AD9637BCPZ-80 ?40c to +85c 64-lead lead frame chip scale package [lfcsp_vq] cp-64-4 ad9637bcpzrl7-80 ?40c to +85c 64-lead lead fr ame chip scale package [lfcsp_vq] cp-64-4 ad9637-80ebz evaluation board 1 z = rohs compliant part.
ad9637 data sheet rev. 0 | page 38 of 40 notes
data sheet ad9637 rev. 0 | page 39 of 40 notes
ad9637 data sheet rev. 0 | page 40 of 40 notes ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d10215-0-10/11(0)

▲Up To Search▲

Price & Availability of AD9637BCPZ-80

	To Download AD9637BCPZ-80 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .